1. Infineon
  2. Microcontroller
  3. 32-bit TriCore™ Microcontroller
  4. 32-bit TriCore™ AURIX™ – TC2xx
  5. AURIX™ Family – TC26xD

Infineon TC267D40F200NBCKXUMA1

SAK-TC267D-40F200N BC belongs to the AURIX™ TC26xD family. Its innovative multicore architecture, based on up to three independent 32-bit TriCore CPUs, has been designed to meet the highest safety standards, while simultaneously increasing performance significantly. Products of the TC26xD are equipped with a dual TriCore with up to 200 MHz, a single voltage supply of 5V or 3.3V and a Powerful Generic Timer Module (GTM) to aim for reduced complexity, best-in-class power consumption and significant cost savings.

Symbol

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Footprint

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3D Model

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Symbol Views

(not all views will be available for every part)

Normal: Standard and most popular representation of schematic symbol

ALT_1 (IEEE view): Symbol representation in a way that is more graphical in explaining what the purpose of each pin is. For connectors and most discretes (as we use these views) it is simply an alternate view for people to use depending on the situation. For instance connectors can be generally an input, an output or neither. Resistors can be vertical or horizontal.

ALT_2 (demorgan): Demorgan is a name for an equivalent Gate structure. so for instance an AND gate and an OR gate can be represented by its Demorgan equivalent of a NOR gate.

Sometimes a device is fractured into multiple symbols (often for high pin count parts). If that is the case, you can preview the different symbols that make up the device by selecting them in this drop down.

Footprint Views

(not all views will be available for every part)

Basic: Our standard footprint view showing, contact area, pin number, top, top assembly

Detailed: Additional info to help you evaluate the part and the footprint including: dimension, silkscreen, soldermask, and solderpaste

PinDetail: Highlights the pin to pad contact area dimensions

Displays min/typ/max pad sizes for footprint per IPC specification (not all sizes will be available for every part)

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