Lattice LIF-MD6000-6JMG80I

iCE40 Series 184320 Bit RAM 36 I/O 1.14 to 1.26 V CrossLink™ FPGA - ctfBGA-80

Symbol

Lattice LIF-MD6000-6JMG80I - Schematic Symbol Schematic Symbol of Lattice LIF-MD6000-6JMG80I showing how CAD model looks and operates before user downloads A1 DPHY1_DN2 A2 DPHY1_DN0 A3 DPHY1_CKN A4 DPHY1_DN1 A5 DPHY1_DN3 A6 DPHY0_DN2 A7 DPHY0_DN0 A8 DPHY0_CKN A9 DPHY0_DN1 B1 DPHY1_DP2 B2 DPHY1_DP0 B3 DPHY1_CKP B4 DPHY1_DP1 B5 DPHY1_DP3 B6 DPHY0_DP2 B7 DPHY0_DP0 B8 DPHY0_CKP B9 DPHY0_DP1 C1 GND C2 GNDA_DPHY1 C9 GNDA_DPHY0 D1 PB48 D2 VCCPLL_DPHY1 D4 VCCA_DPHY1 D5 VCCAUX D6 GNDPLL_DPHYx D7 VCCPLL_DPHY0 D9 PB16A E1 PB34A E2 PB34B E4 VCC E5 GND E6 VCC E7 VCCA_DPHY0 E9 PB12A F1 PB38A F2 PB38B F4 VCCIO0 F5 VCCIO1 F6 VCCIO2 F7 VCCIO2 F9 PB6A G1 PB50 G2 GND G4 VCCIO1 G5 GND G6 VCCGPLL G7 GNDGPLL G9 PB2A H1 PB52 H2 CRESET_B H9 PB2D J1 PB53 J2 PB49 J3 PB34D J4 PB29D J5 PB34D J6 PB29D J7 PB29A J8 PB16D J9 PB6D K1 PB51 K2 PB47 K3 PB43C K4 PB38C K5 PB34C K6 PB29C K7 PB29B K8 PB16C K9 PB12D A10 DPHY0_DN3 B10 DPHY0_DP3 C10 GND D10 PB16B E10 PB12B F10 PB6B G10 PB2B H10 PB2C J10 PB6C K10 PB12C

Footprint

Lattice ctfBGA80_LAT - PCB Footprint / Land Pattern PCB Footprint / Land Pattern of Lattice ctfBGA80_LAT showing how CAD model looks and operates before user downloads A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C9 C10 D1 D2 D4 D5 D6 D7 D9 D10 E1 E2 E4 E5 E6 E7 E9 E10 F1 F2 F4 F5 F6 F7 F9 F10 G1 G2 G4 G5 G6 G7 G9 G10 H1 H2 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 A K 1 10

3D Model

Symbol Views

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Normal: Standard and most popular representation of schematic symbol

ALT_1 (IEEE view): Symbol representation in a way that is more graphical in explaining what the purpose of each pin is. For connectors and most discretes (as we use these views) it is simply an alternate view for people to use depending on the situation. For instance connectors can be generally an input, an output or neither. Resistors can be vertical or horizontal.

ALT_2 (demorgan): Demorgan is a name for an equivalent Gate structure. so for instance an AND gate and an OR gate can be represented by its Demorgan equivalent of a NOR gate.

Sometimes a device is fractured into multiple symbols (often for high pin count parts). If that is the case, you can preview the different symbols that make up the device by selecting them in this drop down.

Footprint Views

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Basic: Our standard footprint view showing, contact area, pin number, top, top assembly

Detailed: Additional info to help you evaluate the part and the footprint including: dimension, silkscreen, soldermask, and solderpaste

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Displays min/typ/max pad sizes for footprint per IPC specification (not all sizes will be available for every part)

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