Lattice LCMXO2-4000ZE-3FTG256I

IC FPGA 206 I/o 256FTBGA


Lattice LCMXO2-4000ZE-3FTG256I_A - Schematic Symbol Schematic Symbol of Lattice LCMXO2-4000ZE-3FTG256I_A showing how CAD model looks and operates before user downloads A1 VCC A2 NC A3 PT12A A4 PT10A A5 PT11A A6 PT13D A7 PT15C A8 PT18B A9 PT20C B1 PL2C B2 GND B3 PT9C B4 PT12B B5 PT9B B6 PT11B B7 PT14A B8 PT15D B9 PT21A C1 PL4C C2 PL2D C3 GND C4 PT9A C5 PT10B C6 PT13C C7 PT14B C8 PT18A C9 PT20D D1 PL3B D2 PL4D D3 PL3A D4 GND D5 VCCIO0 D6 PT13A D7 PT14D D8 PT19A D9 PT20B E1 PL6A E2 PL4A E3 PL4B E4 VCCIO5 E5 GND E6 PT14C E7 PT13B E8 PT15B E9 PT19B F1 PL7B F2 PL6B F3 PL7A F4 PL6C F5 PL8C F6 GND F7 PT15A F8 PT20A F9 PT22A G1 PL9A G2 PL8A G3 PL8B G4 PL7D G5 PL7C G6 PL6D G7 VCC G8 VCCIO0 G9 VCCIO0 H1 PL10B H2 PL9B H3 PL10A H4 PL9C H5 PL13C H6 PL8D H7 VCCIO4 H8 GND H9 GND J1 PL10C J2 PL13A J3 PL10D J4 PL13D J5 PL14C J6 PL9D J7 VCCIO4 J8 GND J9 GND K1 PL13B K2 PL14B K3 PL14A K4 PL16C K5 PL17C


Lattice FTBGA256_LAT - PCB Footprint / Land Pattern PCB Footprint / Land Pattern of Lattice FTBGA256_LAT showing how CAD model looks and operates before user downloads A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 A T 1 16

3D Model

Symbol Views

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Normal: Standard and most popular representation of schematic symbol

ALT_1 (IEEE view): Symbol representation in a way that is more graphical in explaining what the purpose of each pin is. For connectors and most discretes (as we use these views) it is simply an alternate view for people to use depending on the situation. For instance connectors can be generally an input, an output or neither. Resistors can be vertical or horizontal.

ALT_2 (demorgan): Demorgan is a name for an equivalent Gate structure. so for instance an AND gate and an OR gate can be represented by its Demorgan equivalent of a NOR gate.

Sometimes a device is fractured into multiple symbols (often for high pin count parts). If that is the case, you can preview the different symbols that make up the device by selecting them in this drop down.

Footprint Views

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Detailed: Additional info to help you evaluate the part and the footprint including: dimension, silkscreen, soldermask, and solderpaste

PinDetail: Highlights the pin to pad contact area dimensions

Displays min/typ/max pad sizes for footprint per IPC specification (not all sizes will be available for every part)

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